Achronix Speedster22i Clock and Reset Networks - Manual (Page 21)

UG027, May 21, 2014 21
Boundary Clock Network
The boundary clock network is an architectural feature available in Speedster22iHD FPGAs
to help improve IO ring performance in high speed applications. There are two variants of
the boundary clock network: The first is a global boundary clock network, which ensures that
clocks coming in from all 4 sides of the device traverse a muxing network that provides for
low skew between them. The second is a local boundary clock network, which is a shortened
and more direct low jitter path from the CGs to the IO ring resources that need to be clocked.
The main advantages provided by the boundary clock network are as follows:
1. Resources clocked in the IO ring have much higher noise immunity to noise from the
fabric. The IO ring and boundary clock network are on a separate supply from the
rest of the core fabric, so even with very high core resource usage and toggle, power
supply noise is essentially eliminated.
2. Usage of the local boundary clock network provides for a much cleaner, lower jitter,
lower insertion delay path from the CGs to the IO ring resources.
3. Availability of additional clocking resources in the boundary frees up the core clock
network resources to be used for clocking in the fabric.
The main drawbacks of the local boundary clock network are that (a) usage of the different
local boundary clock networks requires more clocks coming into the different CG corners,
and (b) it provides for clocks that can have significant skew between them. Figure 12 below
shows a high-level illustration of the distinction between global and local boundary clock
networks.
Core Fabric
GCG GCG
GCG GCG
GCM
QCM
RCM
BCM
Core Fabric
GCG GCG
GCG GCG
GCM
BCM
Example Global Boundary Clock Network Example Local Boundary Clock Network
Figure 12: Distinction Between Global and Local Boundary Clock Networks
There are four levels of hierarchy and muxing in the boundary clock network. These are, in
hierarchical order: