Achronix Speedster22i Clock and Reset Networks - Manual (Page 12)

12 UG027, May 21, 2014
The PLL contains the following major blocks: reference clock divider, feedback divider,
sigma-delta modulator, phase rotator with divider, mux to select internal or external
feedback signal, phase-frequency detector, charge pump, loop filter and VCO.
The input reference clock can be divided by the reference clock divider. The divider ratio (M)
range is 1 to 63 with 50% duty-cycle. This PLL only supports reference clock range of 30MHz
to 400MHz (after reference clock divider frequency).
The feedback divider ratio (Q) range is 2 to 255 in integer mode with 50% duty cycle. In
fractional mode, the PLL supports 8 to 254 in the integer part. The fractional part (F)
resolution is 16-bit, which is generated by a sigma-delta modulator.
The phase rotator can shift the output clock phase by 1/8th of the internal VCO clock period
at a time. It contains a 50% duty cycle divider with ratio (N) of 1 to 63. The phases of each of
the 4 phase rotators can be independently adjusted, so can the divider ratios. All 4 phase
rotator’s phase can be re-set simultaneously.
The VCO is a 4-stage differential ring oscillator with 8-phase outputs. The VCO also has a
extra divide-by-2 option circuit for process variation backup purpose. It can be turned on in
case the process is too fast.
The PLL reference clock can come from any of the 6 IO buffers in the same CG, or from any
of the four outputs of the preceding PLL. E.g., the rclk of PLL 1 can be driven by PLL 0 (the
order is 0 -> 1 -> 2 -> 3 -> 0). The PLL reference clock is divided by the reference clock divider
(6-bit: 1 to 63) before being sent to the PFD. The VCO generates 8 equally separated phases,
one of which is sent to the feedback divider through a mux to allow the PLL running in short
loop operation without de-skew. All 8-phases are sent to 6 phase rotators which can
independently select one of the 8 phases. This then goes through an output divider (6-bit: 1 to
63) before being sent out of the PLL block. One of the 4 output clocks, after going through the
clock distribution tree, has an option to be sent to the feedback divider for de-skew
functionality.
The PLL has 3 modes of feedback clock selection:
1. Internal feedback mode: the VCO clock is divided by the feedback divider only. In this
mode, the PLL can have both integer and fractional divider ratios. But the PLL does not
provide deskew capability. The VCO frequency is related to the reference clock frequency
through: Fvco=(Q/M)*Fref in integer mode, and Fvco=(Q.F/M)*Fref in fractional mode.
2. External feedback mode: the VCO clock is divided by the output divider inside the phase
rotator. Only the integer divider ratio is supported. The output clock from one of the phase
rotators is sent to downstream logic. After being consumed by the downstream logic, the
clock is fed back to PLL for deskew. Please note in this mode, it is recommend to not rotate
the phase rotator in the feedback path, if the lock signal is required to be high during the
operation because the phase rotator action introduces phase errors to the PLL, and could lead
to the PLL losing lock. The other 5 phase rotators can be used for rotating the phase. The
VCO frequency is related to the reference clock frequency through: Fvco=(N/M)*Fref.
3. Mixed feedback mode: This mode should only be used when the output divider range is
not enough. The VCO is divided by the output divider inside one of the phase rotators. The
output clock from the phase rotator goes to the downstream logic. The consumed clock is
sent back to the PLL for deskew. The feedback clock is sent to the feedback divider before it is
sent to PFD. Only the integer mode of the feedback divider ratio should be used in this mode.
The VCO frequency is related to the reference clock frequency through: Fvco=(Q*N/M)*Fref.