Achronix Speedster22i Clock and Reset Networks - Manual (Page 23)

UG027, May 21, 2014 23
Clock Setting and Reporting
Much of the decision making and optimization for clock selection is automatically done by
the ACE tool to prevent no-routes. However, ACE does provide users with some options to
specify the type of clock networks they wish to use for particular implementations.
The clock type can be specified for a particular CG output in the sdc file as shown below. The
three options available are: {trunk, direct_trunk, boundary}.
Set_clock_type –direct_trunk {‘Hierarchical name of CG output’}
Trunk and direct_trunk correspond to the global and direct core clock networks, respectively.
For the boundary clock network, ACE will automatically decide whether to use the global or
local boundary clock network depending on placement and the application.
Once the clock constraints are specified in the design and the design goes through a full ACE
compilation flow, the routing step outputs text and html files called
“{design_name}_clocks_routed” describing the clock relationships, clock constraints and
clock regions in the design. The clock regions section provides detailed information on how
each of the clocks in the design were routed and how they are distributed in the used FPGA
clock regions, including the boundary. A legend is also provided in the file to help decipher
the routing details.