Switching characteristics - serial audio ports, Figure 1. audio port master mode timing – Cirrus Logic CS8415A User Manual
Page 8
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DS470F4
CS8415A
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
L
= 20 pF.
7.
The active edges of OSCLK are programmable.
8.
The polarity OLRCK is programmable.
9.
No more than 128 SCLK per frame.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
Parameter
Symbol Min Typ
Max
Units
OSCLK Active Edge to SDOUT Output Valid
t
dpd
-
-
20
ns
Master Mode
RMCK to OSCLK active edge delay
t
smd
0
-
10
ns
RMCK to OLRCK delay
t
lmd
0
-
10
ns
OSCLK and OLRCK Duty Cycle
-
50
-
%
Slave Mode
OSCLK Period
t
sckw
36
-
-
ns
OSCLK Input Low Width
t
sckl
14
-
-
ns
OSCLK Input High Width
t
sckh
14
-
-
ns
OSCLK Active Edge to OLRCK Edge
(Note
t
lrckd
20
-
-
ns
OLRCK Edge Setup Before OSCLK Active Edge
t
lrcks
20
-
-
ns
t
sm d
t
lm d
H a rd w a re M o d e
S o ftw a re M o d e
O S C L K
(o u tp u t)
O L R C K
(o u tp u t)
R M C K
(o u tp u t)
R M C K
(o u tp u t)
sckh
sckl
sckw
t
t
t
tdpd
SDOUT
(input)
(input)
lrcks
t
lrckd
t
OSCLK
OLRCK
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing