Cirrus Logic CS8415A - Manual (Page 38)

38 DS470F4
CS8415A
14.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER
MANAGEMENT
14.1 AES3 Channel Status (C) Bit Management
The CS8415A contains sufficient RAM to store a full block of C data for both A and B channels (192 x 2 =
384 bits), and also 384 bits of U information. The user may read from these buffer RAMs through the control
port.
The buffering scheme involves 2 block-sized buffers, named D and E, as shown in Figure 16 . The MSB of
each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at
control port address 20h) is the consumer/professional bit for channel status block A.
The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks
of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the C data.
14.2 Accessing the E Buffer
The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of
the CS8415A, through the control port.
The user can configure the interrupt enable register to cause interrupts to occur whenever D-to-E buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is a D-to-E inhibit bit. This may be used whenever “long” control port interactions are occur-
ring.
Control Port
From
AES3
Receiver
E
24
words
8-bits 8-bits
A B
D
Received
Data
Buffer
Figure 16. Channel Status Data Buffer Structure