3 clock source control (04h), 4 serial audio output port data format (06h), Cs8415a – Cirrus Logic CS8415A User Manual
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DS470F4
CS8415A
MUX2:0 - 7:1 S/PDIF Input Multiplexer Select Line Control
Default = ‘000’
000 - RXP0
001 - RXP1
010 - RXP2
011 - RXP3
100 - RXP4
101 - RXP5
110 - RXP6
111 - Reserved
8.3
Clock Source Control (04h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control reg-
ister, various Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8415A to be placed in a “powered down”, low current
consumption, state.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational,
allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Pow-
er consumption is low.
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8415A to begin operation.
All input clocks should be stable in frequency and phase when RUN is set to 1.
8.4
Serial Audio Output Port Data Format (06h)
SOMS - Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
SOSF - OSCLK frequency (for master mode)
Default = ‘0’
0 - 64*Fs
1 - 128*Fs
SORES1:0 - Resolution of the output data on SDOUT
Default = ‘00’
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits, the time slot
7
6
5
4
3
2
1
0
0
RUN
0
0
0
0
0
0
7
6
5
4
3
2
1
0
SOMS
SOSF
SORES1
SORES0
SOJUST
SODEL
SOSPOL
SOLRPOL