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Aes3 receiver, 1 7:1 s/pdif input multiplexer, 2 omck system clock mode – Cirrus Logic CS8415A User Manual

Page 15: 3 pll, jitter attenuation, and varispeed, 4 error reporting and hold function

Aes3 receiver, 1 7:1 s/pdif input multiplexer, 2 omck system clock mode | 3 pll, jitter attenuation, and varispeed, 4 error reporting and hold function | Cirrus Logic CS8415A User Manual | Page 15 / 46 Aes3 receiver, 1 7:1 s/pdif input multiplexer, 2 omck system clock mode | 3 pll, jitter attenuation, and varispeed, 4 error reporting and hold function | Cirrus Logic CS8415A User Manual | Page 15 / 46
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