Cirrus Logic CS61583 User Manual

Page 31

APPLICATIONS

Line Interface

Figure A1 illustrates a typical connection diagram
and Table A1 lists the external components that
are required in T1 and E1 applications.

In the transmit line interface circuitry, capacitors
C1 and C2 provide transmitter return loss. The
0.47

F capacitor in series with the transformer

primary prevents output stage imbalances from
producing a DC current through the transformer
that might saturate the transformer and result in
an output level offset.

In the receive line interface circuitry, resistors R1-
R4 provide receive impedance matching and
receiver return loss. The 0.47

F capacitor to

ground provides the necessary differential input
voltage reference for the receiver.

Power Supply

As shown in Figure A1, the CS61583 operates
from a 5.0 Volt supply. Separate analog and digi-
tal power supply and ground pins provide internal
isolation. The TGND, RGND, and DGND ground
pins must not be more negative than AGND. It is
recommended that all of the supply pins be con-
nected together at the device. A 4.99k

Ω ±

AV+ AGND1:2 BGREF

TV+1

TGND1

RV+1 RGND1 DV+ DGND1:3

0.01

TCLK1
TPOS1 (TDATA1)
TNEG1 (AIS1)
RCLK1
RPOS1 (RDATA1)
RNEG1 (BPV1)

TCLK2
TPOS2 (TDATA2)
TNEG2 (AIS2)
RCLK2
RPOS2 (RDATA2)
RNEG2 (BPV2)

Framer

TTIP1

TRING1

1:1.15

RTIP1

RRING1

TTIP2

TRING2

RTIP2

RRING2

1:1.15

Hardware Control

Power Supply

Clock Generator

Channel 2

Channel 1

transmit

0.1

TV+2

TGND2

RV+2

RGND2

0.1

1:1.15

receive

1:1.15

receive

R3
4.99k

Ω

0.47

REFCLK 1XCLK

RESET

CLKE

TAOS1

LLOOP1

RLOOP1

CON01

CON11

CON21

RLOOP2

LLOOP2

TAOS2

CON02

CON12

CON22

AMI2

AMI1

CODER2

CODER1

ATTEN1

ATTEN2

0.47

Figure A1. Typical Connection Diagram

Data Rate (MHz)

REFCLK Frequency (MHz)

Cable (

Ω

)

R1-R4 (

Ω

)

C1-C2 (pF)

1XCLK = 1

1XCLK = 0

1.544

12.352

100

38.3

220

2.048

16.384

28.7

470

120

45.3

220

Table A1. CS61583 External Components

CS61583

DS172PP5