Cirrus Logic CS61583 - Manual (Page 19)

The test data register selected by the current in-
struction retains its previous value during this
state. The instruction does not change in this
state.
Pause-DR State
The pause state allows the test controller to tem-
porarily halt the shifting of data through the test
data register in the serial path between J-TDI and
J-TDO. For example, this state could be used to
allow the tester to reload its pin memory from
disk during application of a long test sequence.
The test data register selected by the current in-
struction retains its previous value during this
state. The instruction does not change in this
state.
The controller remains in this state as long as
J-TMS is low. When J-TMS goes high and a
rising edge is applied to J-TCK, the controller
moves to the Exit2-DR state.
Exit2-DR State
This is a temporary state. While in this state, if
J-TMS is held high, a rising edge applied to J-
T C K c au s es t h e c on t rol ler to enter the
Update-DR state, which terminates the scanning
process. If J-TMS is held low and a rising edge
is applied to J-TCK, the controller enters the
Shift-DR state.
The test data register selected by the current in-
struction retains its previous value during this
state. The instruction does not change in this
state.
Update-DR State
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the
TAP controller is in this state and the Boundary
Scan Register is selected, data is latched into the
parallel output of this register from the shift-reg-
ister path on the falling edge of J-TCK. The
data held at the latched parallel output changes
only in this state.
All shift-register stages in the test data register
selected by the current instruction retains their
previous value during this state. The instructions
does not change in this state.
Select-IR-Scan State
This is a temporary controller state. The test
data register selected by the current instruction
retains its previous state. If J-TMS is held low
and a rising edge is applied to J-TCK when in
this state, the controller moves into the Capture-
IR state, and a scan sequence for the instruction
register is initiated. If J-TMS is held high and a
rising edge is applied to J-TCK, the controller
moves to the Test-Logic-Reset state. The in-
struction does not change in this state.
Capture-IR State
In this controller state, the shift register con-
tained in the instruction register loads a fixed
value of "01" on the rising edge of J-TCK. This
supports fault-isolation of the board-level serial
test data path.
Data registers selected by the current instruction
retain their value during this state. The instruc-
tions does not change in this state.
When the controller is in this state and a rising
edge is applied to J-TCK, the controller enters
the Exit1-IR state if J-TMS is held high, or the
Shift-IR state if J-TMS is held low.
Shift-IR State
In this state, the shift register contained in the
instruction register is connected between J-TDI
and J-TDO and shifts data one stage towards its
serial output on each rising edge of J-TCK.
CS61583
DS172PP5 19