Cirrus Logic CS470xx - Manual (Page 19)

19 DS787PP9
5.13 Digital Switching Characteristics–Digital Audio Slave Input Port
5.13 Digital Switching Characteristics–Digital Audio Slave Input Port
Figure 5-8. Digital Audio Input (DAI) Port Timing Diagram
5.14 Digital Switching Characteristics–Digital Audio Output Port
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_
LRCLK.
3. The DAO_LRCLK transition can occur on either side of the edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is
valid.
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
Figure 5-9. DAO_LRCLK Transition before DAO_SCLK Inactive Edge
Parameter Symbol Min Max Unit
DAI_SCLK period T
daiclkp
20 — ns
DAI_SCLK duty cycle — 45 55 %
Setup time DAI_DATAn t
daidsu
8 — ns
Hold time DAI_DATAn t
daidh
5 — ns
Parameter Symbol Min Max Unit
DAO_MCLK period T
daomclk
20 — ns
DAO_MCLK duty cycle — 45 55 %
DAO_SCLK period for Master or Slave mode 1 T
daosclk
20 — ns
DAO_SCLK duty cycle for Master or Slave mode 1 — 40 60 %
Master Mode (Output A1 Mode) 1,2
DAO_SCLK delay from DAO_MCLK rising edge, DAO MCLK as an input t
daomsck
— 19 ns
DAO_LRCLK to DAO_SCLK inactive edge 3 . See Fig. 5-9 . t
daomlrts
— 8 ns
DAO_SCLK inactive edge 3 to DAO_LRCLK. See Fig. 5-10 . t
daomstlr
— 8 ns
DAO_DATA[3:0] delay from DAO_SCLK inactive edge 3 t
daomdy
— 8 ns
Slave Mode (Output A0 Mode) 4
DAO_SCLK active edge to DAO_LRCLK transition. See Fig. 5-11 . t
daosstlr
10 — ns
DAO_LRCLK transition to DAO_SCLK active edge. See Fig. 5-12 . t
daoslrts
10 — ns
DAO_Dx delay from DAO_SCLK inactive edge t
daosdv
— 11 ns
DAI_SCLK
DAI_DATAn
t
daidh
t
daidsu
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAO_DATAn
t
daomsck
t
daomlrts
t
daomdv
t
daomclk