Cirrus Logic CS470xx - Manual (Page 15)

15 DS787PP9
5.8 Digital Switching Characteristics–Internal Clock
5.8 Digital Switching Characteristics–Internal Clock
1. After initial power-on reset, F
dclk
= F
xtal
. After initial kick-start commands, the PLL is locked to max F
dclk
and remains locked until the next power-on
reset.
2. See Section 5.7 . for all references to F
xtal
.
5.9 Digital Switching Characteristics–Serial Control Port–SPI Slave Mode
1. f
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication
port can be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data
buffer. At boot the maximum speed is F
xtal
/3.
Parameter Symbol
Min (2-
layer Boards)
Min (4-
layer Boards)
Max (2-
layer Boards)
Max (4-
layer Boards)
Unit
Internal DSP_CLK frequency 1
CS47048-CQZ
CS47048-DQZ
CS47028-CQZ
CS47028-DQZ
CS47024-CQZ
CS47024-DQZ
F
dclk
(See Footnote 2)
F
xtal
F
xtal
F
xtal
F
xtal
F
xtal
F
xtal
147
131
147
131
147
131 147
147
147
147
147
147
MHz
Internal DSP_CLK period 1
CS47048-CQZ
CS47048-DQZ
CS47028-CQZ
CS47028-DQZ
CS47024-CQZ
CS47024-DQZ
DCLKP
6.8
7.6
6.8
7.6
6.8
7.6 6.8
6.8
6.8
6.8
6.8
6.8 1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
ns
Parameter Symbol Min Typical Max Unit
SCP_CLK frequency 1 f
spisck
— — 25 MHz
SCP_CS falling to SCP_CLK rising t
spicss
24 — — ns
SCP_CLK low time t
spickl
20 — — ns
SCP_CLK high time t
spickh
20 — — ns
Setup time SCP_MOSI input t
spidsu
5 — — ns
Hold time SCP_MOSI input t
spidh
5 — — ns
SCP_CLK low to SCP_MISO output valid t
spidov
— — 11 ns
SCP_CLK falling to SCP_IRQ rising t
spiirqh
— — 27 ns
SCP_CS rising to SCP_IRQ falling t
spiirql
0 — — ns
SCP_CLK low to SCP_CS rising t
spicsh
24 — — ns
SCP_CS rising to SCP_MISO output high-Z t
spicsdz
— 20 — ns
SCP_CLK rising to SCP_BSY falling t
spicbsyl
— 3*DCLKP+20 — ns