Cirrus Logic CS470xx - Manual (Page 16)

DS787PP9 16
5.10 Digital Switching Characteristics–Serial Control Port–SPI Master
Figure 5-4. Serial Control Port–SPI Slave Mode Timing
5.10 Digital Switching Characteristics–Serial Control Port–SPI Master Mode
1. f
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication
port can be limited by the firmware application.
2. See Section 5.7.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
Parameter Symbol Min Typical Max Units
SCP_CLK frequency 1,2 f
spisck
— — F
xtal
/2 MHz
EE_CS falling to SCP_CLK rising 3 t
spicss
— 11*DCLKP+(SCP_CLK PERIOD)/2 — ns
SCP_CLK low time t
spickl
18 — — ns
SCP_CLK high time t
spickh
18 — — ns
Setup time SCP_MISO input t
spidsu
9 — — ns
Hold time SCP_MISO input t
spidh
5 — — ns
SCP_CLK low to SCP_MOSI output valid t
spidov
— — 8 ns
SCP_CLK low to EE_CS falling t
spicsl
7 — — ns
SCP_CLK low to EE_CS rising t
spicsh
— 11*DCLKP+(SCP_CLK PERIOD)/2 — ns
Bus free time between active EE_CS t
spicsx
— 3*DCLKP — ns
SCP_CLK falling to SCP_MOSI output high-Z t
spidz
— — 20 ns
SCP_BSY
SCP_CS
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ
0 1 2 6 7 0 5 6 7
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh
t
spidov
A6 A5 A0 R/W MSB LSB
MSB LSB
t
spicsh
t
spibsyl
t
spiirql
t
spiirqh
f
spisck
t
spicsdz
1/