Cirrus Logic CS470xx - Manual (Page 18)

DS787PP9 18
5.12 Digital Switching Characteristics–Serial Control Port–I2C Master
Figure 5-6. Serial Control Port–I 2 C Slave Mode Timing
5.12 Digital Switching Characteristics–Serial Control Port–I 2 C Master Mode
1. f
iicck
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication
port can be limited by the firmware application.
Figure 5-7. Serial Control Port–I 2 C Master Mode Timing
Parameter Symbol Min Max Units
SCP_CLK frequency 1 f
iicck
— 400 kHz
SCP_CLK rise time t
iicr
— 150 ns
SCP_CLK fall time t
iicf
— 150 ns
SCP_CLK low time t
iicckl
1.25 — µs
SCP_CLK high time t
iicckh
1.25 — µs
SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition t
iicckcmd
1.25 — µs
START condition to SCP_CLK falling t
iicstscl
1.25 — µs
SCP_CLK falling to STOP condition t
iicstp
2.5 — µs
Bus free time between STOP and START conditions t
iicbft
3 — µs
Setup time SCP_SDA input valid to SCP_CLK rising t
iicsu
110 — ns
Hold time SCP_SDA input after SCP_CLK falling t
iich
100 — ns
SCP_CLK low to SCP_SDA out valid t
iicdov
— 36 ns
SCP_BSY
SCP_CLK
SCP_SDA
SCP_IRQ
0 1 6 7 8 0 1 7
t
iicckl
t
iicckh
t
iicsu
t
iich
A6 A0 R/W ACK LSB
t
iicirqh t
iicirql
8
ACK MSB
t
iicstp
6
t
iiccbsyl
t
iicdov
t
iicbft
t
iicstscl
t
iicckcmd
f
iicck
t
iicckcmd
t
iicf
t
iicr
Start Condition
1/
Stop Condition
SCP_CLK
SCP_SDA
0 1 6 7 8 0 1 7
t
iicckl
t
iicckh
t
iicsu
t
iich
A6 A0 R/W ACK LSB
8
ACK MSB
t
iicstp
6
t
iicdov
t
iicbft
t
iicstscl
t
iicckcmd
f
iicck
t
iicckcmd
t
iicf
t
iicr
1/