Cirrus Logic CS470xx - Manual (Page 10)

DS787PP9 10
4.3 On-chip DSP Peripherals
4.3.2 Digital to Analog Converter Port (DAC)
The DACs in the CS470xx devices feature dynamic range performance in excess of 100 dB. See Section 5.17 for more
details on CS470xx DAC performance. The CS47024 device supports four simultaneous channels of digital-to-analog
conversion. The CS47028 and CS47048 devices provide eight simultaneous channels of digital-to-analog conversion. The
DACs have voltage mode outputs that can be connected either as single-ended or differential signals. The conversions
are performed with Fs=96 kHz.
4.3.3 Digital Audio Input Port (DAI)
The input capabilities for each version of the CS470xx are summarized in Table 3-1 and Table 3-2 .
Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other functions. If the SPI mode
is used, the DAI_DATA4 pin becomes the SCP_CS input. The integrated S/PDIF receiver can be used to take over the
DAI_DATA3 pin.
The DAI port PCM inputs have a single slave-only clock domain. The S/PDIF receiver, if used, is a separate clock domain.
The output of the S/PDIF Rx can then be converted through one of the internal SRC blocks to synchronize with the PCM
input. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of
monitoring the S/PDIF Rx from the host. A time-stamping feature provides the ability to also sample-rate convert the input
data via software.The DAI port supports PCM format with word lengths up to 32 bits and sample rates as high as 192 kHz.
The DAI also supports a time division multiplexed (TDM) mode that packs up to 10 PCM audio channels on a single data
line.
4.3.4 S/PDIF RX Input Port (DAI)
One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input capable of receiving and
demodulating bi-phase encoded S/PDIF signals with Fs < 192 kHz.
4.3.5 Digital Audio Output Port (DAO)
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port
can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/
LRCLK source is available.
The DAO also supports a time division multiplexed (TDM) mode, that packs up to 8 channels of PCM audio on a single
data line.
4.3.6 S/PDIF TX Output Port (DAO)
Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded S/PDIF signal (data
with embedded clock on a single line).
4.3.7 Sample Rate Converters (SRC)
All CS470xx devices have at least two internal hardware SRC modules. One is directly associated with the ADCs and
normally serves to convert data from the 96 kHz sampling rate of the ADCs to another Fs appropriate for mixing with other
audio in the system.
The other SRC module is directly associated with the DACs and normally serves to convert data from the DSP into the 96
kHz sample rate needed by the DACs.
The CS47024, CS47028, and CS47048 devices have an additional stand-alone 8-channel SRC module. This SRC module
can be used to make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx).