Cirrus Logic CS470xx - Manual (Page 17)

17 DS787PP9
5.11 Digital Switching Characteristics–Serial Control Port I2C Slave Mode
Figure 5-5. Serial Control Port–SPI Master Mode Timing
5.11 Digital Switching Characteristics–Serial Control Port I 2 C Slave Mode
1. f
iicck
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication
port can be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data
buffer.
I 2 C Slave Address = 0x82
Parameter Symbol Min Typical Max Units
SCP_CLK frequency 1 f
iicck
— — 400 kHz
SCP_CLK rise time t
iicr
— — 150 ns
SCP_CLK fall time t
iicf
— — 150 ns
SCP_CLK low time t
iicckl
1.25 — — µs
SCP_CLK high time t
iicckh
1.25 — — µs
SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition t
iicckcmd
1.25 — — µs
START condition to SCP_CLK falling t
iicstscl
1.25 — — µs
SCP_CLK falling to STOP condition t
iicstp
2.5 — — µs
Bus free time between STOP and START conditions t
iicbft
3 — — µs
Setup time SCP_SDA input valid to SCP_CLK rising t
iicsu
110 — — ns
Hold time SCP_SDA input after SCP_CLK falling t
iich
100 — — ns
SCP_CLK low to SCP_SDA out valid t
iicdov
— — 18 ns
SCP_CLK falling to SCP_IRQ rising t
iicirqh
— — 3*DCLKP+40 ns
NAK condition to SCP_IRQ low t
iicirql
— 3*DCLKP+20 — ns
SCP_CLK rising to SCB_BSY low t
iicbsyl
— 3*DCLKP+20 — ns
EE_CS
SCP_CLK
SCP_MISO
SCP_MOSI
0 1 2 6 7 0 5 6 7
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh
t
spidov
A6 A5 A0 R/W MSB LSB
MSB LSB
t
spicsh
t
spicsx
f
spisck
t
spidz
t
spicsl
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