Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 9)

• MP_02
IUT always asserts all byte enables during each data phase of a Memory Write Invalidate
cycle. (3.1.1)
In this test a memory write and invalidate command with two data phases must be executed by
IUT.
• MP_03
IUT always uses Linear Burst Ordering for Memory Write Invalidate cycles. (3.1.1)
Like previous test a memory write and invalidate command with two data phases must be executed.
The memory address of this test is incremented by one, e.g. 10000001H.
Compliance Test
9 Rev. 1.0