Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 27)

• 1.02
PCI BUS SINGLE DATA PHASE TARGET ABORT CYCLES
The transactions of this section are similar to the previous section (1.01) with the exception that the
memory and configuration sets are repeated three times instead of four, the I/O set is repeated two
times on active boards and three times on passive boards and the special cycle is not needed.
Medium Speed Memory Read
Medium Speed Memory Write
Slow Speed Memory Read
Compliance Test
27 Rev. 1.0