Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 7)

MP_XX
General Component Protocol checklist(master)
Most requests are for only one transaction as indicated here, these transactions may be a single word or
a burst transfer. In this example a memory write and invalidate command with two data phases is
requested.
The user may change the data in the white fields. For 32 bit bus set the upper bits to 00000000.
Some requests require several transactions. In this example first a memory read and then two memory
writes with different data are requested.
Sometimes the user is requested to confirm the result at the end of the test.
Compliance Test
7 Rev. 1.0