Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 60)

• 1.10
PCI BUS DATA PARITY ERROR MULTI-DATA PHASE CYCLES
In this test seven transactions must be executed. The first is a memory read, the second is a memory
write, the third is a configuration read, the fourth is a configuration write, the fifth is a memory read
multiple, the sixth is a memory read line and the last is a memory write & invalidate. All
transactions have two data phases.
Compliance Test
60 Rev. 1.0