Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 18)

• MP_31
IUT always drives PERR# (when enabled) for a minimum of 1 clock for each data phase that
a parity error is detected. (3.8.2.1)
In this test a memory read command with three data phases must be executed by IUT.
• MP_32
IUT always holds FRAME# asserted for cycle following DUAL command. (3.10.1)
In this test dual address cycle is tested thus the address size must be 64-bit. The low 32-bit is the
free memory address found by TA660 and the high 32-bit is the constant value 0000003bH. The
requested transaction has one data phase.
Compliance Test
18 Rev. 1.0