Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 17)

• MP_28
IUT always drives PAR within one clock of C/BE# and AD being driven. (3.8.1)
In this test three transactions must be executed by IUT all with one data phase. The first transaction
is a memory read, the second is a memory write with data equal to 98765431H and the third is a
memory write with data equal to 98765430H.
• MP_29
Part of MP_28 test group.
• MP_30
IUT always drives PERR# (when enabled) active two clocks after data when data parity error
is detected. (3.8.2.1)
In this test a memory read command with one data phase must be executed by IUT.
Compliance Test
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