Atec Agilent-E8267D - Manual (Page 28)

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Baseband generator Accepts a sine or square wave PECL clock input with a
clock input frequency range of 200 to 400 MHz (resulting in sample
rates of 50 MSa/s to 100 MSa/s). The recommended input
level is approximately 1 V
peak-to-peak
for a square wave and
0 dBm to 6 dBm for a sine wave. Allows the baseband
generators of multiple signal sources to run off same clock.
Burst gate input Accepts signal for gating burst power for use with internal
baseband generator (Option 602). The burst gating
is used when you are externally supplying data and clock
information. The input signal must be synchronized with
the external data input that will be output during the burst.
The burst power envelope and modulated data are internally
delayed and re-synchronized. The input signal must be
CMOS high for normal burst RF power or CW RF output
power and CMOS low for RF off. Damage levels are
> +5.5 V and < –0.5 V.
Event 1 output In real-time mode, outputs a pattern or frame synchronization
pulse for triggering or gating external equipment, for use
with internal baseband generator (Option 602). May
be set to start at the beginning of a pattern, frame, or
timeslot and is adjustable to within ± one timeslot with
one bit resolution. In arbitrary waveform mode, outputs a
timing signal generated by marker 1.
Event 2 output In real-time mode, outputs a data enable signal for gating
external equipment, for use with internal baseband generator
(Option 602). Applicable when external data is clocked into
internally generated timeslots. Data is enabled when signal
is low. In arbitrary waveform mode, outputs a timing signal
generated by marker 2.
I and Q outputs Outputs the analog I/Q modulation signals from the internal
baseband generator. Nominal output impedance 50 Ω,
DC-coupled. Damage levels ±3.5 V.
I and Q outputs Outputs the complement of the I and Q signals for differential
applications. Nominal output impedance 50 Ω, DC-coupled.
Damage levels ±3.5 V.
Pattern trigger input Accepts signal to trigger internal pattern or frame generator
to start single pattern output, for use with internal baseband
generator (Option 602). Minimum pulse width 100 ns.
Damage levels are > +5.5 V and < –0.5 V.
Wideband I and Q inputs Direct differential high-bandwidth analog inputs to I/Q
modulator in 3.2 to 44 GHz range and useable for carriers
< 3.2 GHz.. Not calibrated. 0 dBm maximum.
(Option 016 only).
Removable flash memory Accepts 8 GB compact flash memory card for optional
drive non-volatile memory (Option 009 only). All user
information (save/recall settings, flatness files, presets,
etc.) is stored on removable memory card when
Option 009 is installed.
Alternate power input
Accepts CMOS signal for synchronization of external data
and alternate power signal timing. Damage levels are
> +8 V and < –4V.
Data clock output Relays a CMOS bit clock signal for synchronizing serial data.
Data output Outputs data from the internal data generator or the
externally supplied signal at data input. CMOS signal.
Event 3 output In arbitrary waveform mode, outputs a timing signal generated
by marker 3. Damage levels > +8 V and < 4 V.
Event 4 output In arbitrary waveform mode, outputs a timing signal generated
by marker 4. Damage levels > +8 V and < 4 V.
Symbol sync output Outputs CMOS symbol clock for symbol synchronization,
one data clock period wide.
Auxiliary I/O connector
(37-pin) used with Option 602