Atec Agilent-E8267D - Manual (Page 23)

23
Baseband reference frequency Data clock can be phase locked to an external refer-
ence.
Input
ECL, CMOS, TTL compatible, 50 Ω AC coupled
Frame trigger delay control
Range
0 to 1,048,575 bits
Resolution 1 bit
Data types
Internally generated data
Pseudo-random patterns
PN9, PN11, PN15, PN20, PN23
Repeating sequence Any 4-bit sequence
Other fixed patterns
Direct-pattern RAM [PRAM]
Max size 64 Mb (Option 602)
(each bit uses an entire sample space)
Use Non-standard framing
User file
Max size 6.4 Mb (Option 602)
Use Continuous modulation or internally generated
TDMA standard
Externally generated data
Type
Serial data
Inputs Data, data (bit) clock, symbol sync
Accepts data rates ±5% of specified data rate
Internal burst shape control
Varies with standards and bit rates
Rise/Fall time range
Up to 30 bits
Rise/Fall delay range 0 to 63.5 bits
Spectral re-growth (measured)
10 GHz carrier with 16 QAM signal at 10 Msym/s 25 GHz carrier with 16 QAM signal at 10 Msym/s
Ref-12 dBm
Samp
Log
10
dB/
LgAv
100
W1 S2
S3 FC
£(f):
FTun
Swp
◊Atten 10 dB
∆ Mkr1 12.00 MHz
-64.622 dB
Center 10.000 00 GHz
◊Res BW 470 kHz
VBW 470 kHz
Span 50 MHz
Sweep 1 ms (601 pts)
Marker ∆
12.000000 MHz
-64.622 dB
Ref-10 dBm
Samp
Log
10
dB/
LgAv
100
W1 S2
S3 FC
£(f):
FTun
Swp
◊Atten 0 dB
∆ Mkr1 -12.00 MHz
-60.125 dB
Center 25.000 00 GHz
◊Res BW 300 kHz
VBW 300 kHz
Span 50 MHz
Sweep 2.12 ms (601 pts)
Marker ∆
-12.000000 MHz
-60.125 dB