Rainbow Electronics BR24L02FVM-W - Manual (Page 7)

BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs BR24L02FV-W / BR24L02FVM-W
7/25
zWP timing
SCL
SDA
WP
t HD : WP
t WR
STOP BIT
ACK ACK
D1
DATA (n) DATA (1)
t SU : WP
D0
Fig.6(a) WP TIMING OF THE WRITE OPERATION
SCL
SDA
WP
ACK ACK
D1
DATA (n) DATA (1)
t HIGH : WP
D0
Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION
•
For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
D0 of first byte until the end of t WR . ( See Fig.6 (a) )
During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )
•
In the case of setting WP “HIGH” during t WR , WRITE operation is stopped in the middle and the data of accessing
address is not guaranteed. Please write correct data again in the case.