Rainbow Electronics BR24L02FVM-W - Manual (Page 4)

BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs BR24L02FV-W / BR24L02FVM-W
4/25
zBlock diagram
1 A0
A1 2
A2 3
GND 4
V CC 8
WP 7
6 SCL
SDA 5
2kbit EEPROM array
Control logic
High voltage generator Vcc level detect
8bit 8bit
ACK
STOP START
Address
decoder Slave word
address register
8bits
Data
register
Fig.2 BLOCK DIAGRAM
zPin configuration
BR24L02-W
BR24L02F-W
BR24L02FJ-W
BR24L02FV-W
BR24L02FVM-W
V CC
A0
WP
A1
SCL
A2
SDA
GND
1 2 3 4
5 6 7 8
Fig.3 PIN LAYOUT
zPin name
Write protect input
Power supply
Function
Ground (0V)
Slave address set
Serial clock input
SDA
V CC
A0, A1, A2
Pin name
GND
WP
SCL
I / O
−
−
IN
IN
IN
IN / OUT
Slave and word address,
serial data input, serial data output
∗ 1 An open drain output requires a pull-up resistor.
∗ 1