Adc data register – adcl and adch – Rainbow Electronics AT90LS8535 User Manual

Page 73

AT90S/LS8535

1041H–11/01

ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. When a extended conversion precedes a real conversion,
ADSC will stay high until the real conversion completes. Writing a “0” to this bit has no
effect.

• Bit 5 – ADFR: ADC Free Running Select

When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the
ADC samples and updates the data registers continuously. Clearing this bit (zero) will
terminate Free Running Mode.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set (one) when an ADC conversion completes and the data registers are
updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-
bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond-
ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the
flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be dis-
abled. This also applies if the SBI and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete interrupt is activated.

• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.

ADC Data Register – ADCL
AND ADCH

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-
quently, it is essential that both registers are read and that ADCL is read before ADCH.

Table 28. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

128

Bit

$05 ($25)

–

ADC9

ADC8

ADCH

$04 ($24)

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADCL

Read/Write

Initial Value