Rainbow Electronics AT90LS8535 - Manual (Page 54)

54
AT90S/LS8535
1041H–11/01
Serial Peripheral
Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the AT90S8535 and peripheral devices or between several AVR devices. The
AT90S8535 SPI features include the following:
•
Full-duplex, 3-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End-of-transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
Figure 37. SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in Figure 38.
The PB7(SCK) pin is the clock output in the Master Mode and is the clock input in the
Slave Mode. Writing to the SPI Data Register of the master CPU starts the SPI clock
generator and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)
pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the
end-of-transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR regis-
ter is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to select
an individual slave SPI device. The two shift registers in the master and the slave can be
considered as one distributed 16-bit circular shift register. This is shown in Figure 38.
When data is shifted from the master to the slave, data is also shifted in the opposite
direction, simultaneously. During one shift cycle, data in the master and the slave is
interchanged.