Rainbow Electronics AT45DB081D - Manual (Page 51)

51
3596N–DFLASH–11/2012
AT45DB081D
28. Revision History
Revision Level – Release Date History
A – November 2005 Initial Release
B – March 2006
Added Preliminary.
Added text, in “Programming the Configuration Register”, to indicate
that power cycling is required to switch to “power of 2” page size
after the opcode enable has been executed.
Added “Legacy Commands” table.
C – July 2006
Corrected PA3 in opcode 50h for addressing sequence with
standard page size. Corrected Chip Erase opcode from 7CH to
C7H. Clarified the commands B and C usage for operation mode.
D – November 2006
Removed Preliminary.
Added errata regarding Chip Erase.
Changed various timing parameters under Table 18-4 .
E – February 2007 Removed RDY/BUSY pin references.
F – August 2007
Removed SER/BYTE statement from SI and SO pin descriptions in
Table 2-1.
Added additional text to “power of 2” binary page size option.
Changed t
VSCL
from 50µs to 70µs.
Changed t
RDPD
from 30µs to 35µs.
G – January 2008
Added additional text, in “power of 2” binary page size option, to
indicate that the address format is changed for devices with page
size set to 256-bytes.
Corrected typographical error to indicate that Figure 13-1 indicates
Program Configuration Register.
H – January 2008 Removed DataFlash card pinout.
I – April 2008
Added part number ordering code details for suffixes SL954/955
Added ordering code details.
J – February 2009 Changed t
DIS
(Typ and Max) to 27ns and 35ns, respectively.
K – March 2009
Changed Deep Power-Down Current values
- Increased typical value from 5µA to 15µA.
- Increased maximum value from 15µA to25 µA.
L – April 2009
Updated Absolute Maximum Ratings
Removed Chip Erase Errata
M – May 2010
Changed t
SE
(Typ) 1.6 to 0.7 and (Max) 5 to 1.3
Changed t
CE
(Typ) TBD to 7 and (Max) TBD to 22
Changed from 10,000 to 20,000 cumulative page erase/program
operations and added the contact statement in section 11.3
.
N – November 2010 Update to Adesto.