Rainbow Electronics AT45DB081D - Manual (Page 22)

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3596N–DFLASH–11/2012
AT45DB081D
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit six of the status register. If bit six is a zero, then the data in the main memory page matches
the data in the buffer. If bit six is a one, then at least one bit of the data in the main memory page
does not match the data in the buffer.
Bit one in the Status Register is used to provide information to the user whether or not the sector
protection has been enabled or disabled, either by software-controlled method or hardware-con-
trolled method. A logic one indicates that sector protection has been enabled and logic zero
indicates that sector protection has been disabled.
Bit zero in the Status Register indicates whether the page size of the main memory array is con-
figured for “power of 2” binary page size (256-bytes) or the DataFlash standard page size (264-
bytes). If bit zero is a one, then the page size is set to 256-bytes. If bit zero is a zero, then the
page size is set to 264-bytes.
The device density is indicated using bits five, four, three, and two of the status register. For the
Adesto AT45DB081D, the four bits are 1001 The decimal value of these four binary bits does not
equate to the device density; the four bits represent a combinational code relating to differing
densities of DataFlash devices. The device density is not the same as the density code indicated
in the JEDEC device ID information. The device density is provided only for backward
compatibility.
12. Deep Power-down
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pin (SI). After the last bit of the command has
been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down operation.
After the CS pin is de-asserted, the will device enter the Deep Power-down mode within the
maximum t
EDPD
time. Once the device has entered the Deep Power-down mode, all instructions
are ignored except for the Resume from Deep Power-down command.
Table 12-1. Deep Power-down
Figure 12-1. Deep Power-down
Table 11-1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP 1 0 0 1 PROTECT PAGE SIZE
Command Opcode
Deep Power-down B9H
Opcode
CS
Each transition
represents 8 bits
SI