Rainbow Electronics DS2422 - Manual (Page 42)

DS2422
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The sum of t
RL
+ d (rise rime) on one side and the internal timing generator of the DS2422 on the other side define
the master sampling window (t
MSRMIN
to t
MSRMAX
) in which the master must perform a read from the data line. For
most reliable communication, t
RL
should be as short as permissible and the master should read close to but no later
than t
MSRMAX
. After reading from the data line, the master must wait until t
SLOT
is expired. This guarantees sufficient
recovery time t
REC
for the DS2422 to get ready for the next time slot.
IMPROVED NETWORK BEHAVIOR
In a 1-Wire environment line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points and branch points can add up or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, as a consequence, result in a search ROM
command coming to a dead end or cause a device-specific function command to abort. For better performance in
network applications, the DS2422 uses a new 1-Wire front end, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave device itself.
The 1-Wire front end of the DS2422 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line
impedance than a digitally switched transistor, converting the high frequency ringing known from traditional
devices into a smoother low-bandwidth transition. The slew rate control is specified by the parameter t
FPD
,
which has different values for standard and Overdrive speed.
2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.
3) There is a hysteresis at the low-to-high switching threshold V
TH
. If a negative glitch crosses V
TH
but doesn’t go
below V
TH
- V
HY
, it will not be recognized (Figure 17, Case A). The hysteresis is effective at any 1-Wire speed.
4) There is a time window specified by the rising edge hold-off time t
REH
during which glitches will be ignored,
even if they extend below V
TH
- V
HY
threshold (Figure 17, Case B, t
GL
< t
REH
). Deep voltage droops or glitches
that appear late after crossing the V
TH
threshold and extend beyond the t
REH
window cannot be filtered out and
will be taken as beginning of a new time slot (Figure 17, Case C, t
GL
³ t
REH
).
Only devices which have the parameters t
FPD
, V
HY
and t
REH
specified in their electrical characteristics use the
improved 1-Wire front end.
Figure 17. Noise Suppression Scheme
V
PUP
V
TH
V
HY
0V
t
REH
t
GL
t
REH
t
GL
Case A Case C Case B
CRC GENERATION
With the DS2422 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type
and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the
first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2422 to determine if the ROM data
has been received error-free. The equivalent polynomial function of this CRC is: X
8 + X 5 + X 4 + 1. This 8-bit CRC is
received in the true (non-inverted) form. It is computed at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x 16 + x 15 + x 2
+ 1. This CRC is used for error detection when reading register pages or the datalog memory using the Read
Memory with CRC command and for fast verification of a data transfer when writing to or reading from the
scratchpad. In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC-
generator inside the DS2422 chip (Figure 18) will calculate a new 16-bit CRC as shown in the command flow chart
of Figure 12. The bus master compares the CRC value read from the device to the one it calculates from the data