Rainbow Electronics MAX8760 User Manual
Page 32
MAX8760
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
32
______________________________________________________________________________________
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low V
IN
- V
OUT
differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output
filter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty fac-
tor, which can be calculated from the on-time and mini-
mum off-time. For a dual-phase controller, the
worst-case output sag voltage can be determined by:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics table) and K is from Table 6.
The amount of overshoot due to stored inductor energy
can be calculated as:
where
η
TOTAL
is the total number of active phases.
Setting the Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
LOAD(MAX)
minus
half the ripple current; therefore:
where
η
TOTAL
is the total number of active phases, and
I
LIMIT(LOW)
equals the minimum current-limit threshold
voltage divided by the current-sense resistor (R
SENSE
).
For the 30mV default setting, the minimum current-limit
threshold is 28mV.
Connect ILIM to V
CC
for the default current-limit thresh-
old (see the Electrical Characteristics table). In
adjustable mode, the current-limit threshold is precisely
1/20 the voltage seen at ILIM. For an adjustable thresh-
old, connect a resistive divider from REF to GND with
ILIM connected to the center tap. When adjusting the
current limit, use 1% tolerance resistors with approxi-
mately 10µA of divider current to prevent a significant
increase of errors in the current-limit tolerance.
Output Capacitor Selection
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
In CPU V
CORE
converters and other applications where
the output is subject to large-load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. When operating multiphase systems out-of-
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For 3- or
4-phase operation, the maximum ESR to meet ripple
requirements is:
where
η
TOTAL
is the total number of active phases, t
ON
is the calculated on-time per phase, and t
TRIG
is the trig-
ger delay between the master’s DH rising edge and the
slave’s DH rising edge. The trigger delay must be less
than 1/(f
SW
x
η
TOTAL
) for stable operation. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usual-
ly selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
SAG
and V
SOAR
from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the V
SAG
and V
SOAR
equations
in the Transient Response section).
R
V
L
V
V
t
V
t
ESR
RIPPLE
IN
TOTAL OUT ON
TOTAL OUT TRIG
≤
−
−
(
)
2
η
η
R
V
I
ESR
STEP
LOAD MAX
≤
∆
(
)
I
I
LIR
LIMIT LOW
LOAD MAX
TOTAL
(
)
(
)
>
−
η
1
2
V
I
L
C
V
SOAR
LOAD MAX
TOTAL
OUT OUT
≈
(
)
(
)
∆
2
2
η
V
L I
V
K
V
t
C
V
V
V
K
V
t
I
C
V
K
V
t
SAG
LOAD MAX
OUT
IN
OFF MIN
OUT OUT
IN
OUT
IN
OFF MIN
LOAD MAX
OUT
OUT
IN
OFF MIN
=
−
−
+
+
+
(
)
(
)
(
)
(
)
(
)
(
)
(
)
∆
∆
2
2
2
2
2