Texas Instruments TMS320C6457 - Manual (Page 41)

www.ti.com HPI Registers
8.5 Data Register (HPID)
The 32-bit register HPID provides the data path between the host and the HPI DMA logic. During a host
write cycle, the host fills HPID with 32 bits, and then the HPI DMA logic transfers the 32-bit value to the
internal memory of the DSP. During a host read cycle, the HPI DMA logic fills HPID with 32 bits from the
internal memory, and then the HPI transfers the 32-bit value to the host. A host cycle is a single 32-bit
transfer (in the 32-bit multiplexed mode) or two consecutive 16-bit transfers (in the 16-bit multiplexed
mode).
As shown in Figure 34 , the host has full read/write access to HPID. The CPU cannot access HPID.
In the multiplexed modes, HPID is actually a port through which the host accesses two first-in, first-out
buffers (FIFOs). The read FIFO and the write FIFO play a significant role in providing a higher data
throughput. For information about the FIFOs, see
Section 6 .
Figure 34. Data Register (HPID) (Host access permissions, CPU cannot access HPID)
31-0
DATA
R/W-0
LEGEND: R = Read only; W = Write; -n = Value after hardware reset
Table 10. Data Register (HPID) Field Descriptions
Bit Field Value Description
31-0 DATA HPI data
41 SPRUGK7A – March 2009 – Revised July 2010 Host Port Interface (HPI)
Copyright © 2009–2010, Texas Instruments Incorporated