Texas Instruments TMS320C6457 - Manual (Page 26)

11 10
HPIA Write HPID Read
HCNTL[1:0]
HD[31:0]
HRDY
HR/W
Internal
HSTRB
HCS
10 01 01 01
HPIA Write HPID+ Reads
HD[31:0]
HRDY
HCS A
HCNTL[1:0]
HR/W
Internal
HSTRB
HPI Operation www.ti.com
Figure 20. HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode
(Case 1: HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle)
Figure 21 shows an HPIA (HCNTL[1:0] = 10b) write access followed by several autoincrement HPID
(HCNTL[1:0] = 01b) read accesses. Note that HRDY is active for the HPIA access. HRDY is also active
for the first HPID read access, but not for subsequent read accesses.
Figure 21. HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode
(Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)
A HCS may be brought high during strobe cycles. However, note that HRDY is gated by HCS.
3.9.4 HRDY Behavior During 32-Bit Multiplexed Write Operations
Figure 22 shows an HPIC (HCNTL[1:0] = 00b) write access for 32-bit multiplexed HPI operation. Note that
an HPIC write access does not cause HRDY to become active.
26 Host Port Interface (HPI) SPRUGK7A – March 2009 – Revised July 2010
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