National Instruments DAQCard-1200 - Manual (Page 52)

Chapter 3 Signal Connections
DAQCard-1200 User Manual 3-30 © National Instruments Corporation
Figure 3-19 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the OUT output signals of
the 82C53.
Figure 3-19. General-Purpose Timing Signals
The GATE and OUT signals in Figure 3-19 are referenced to the rising edge
of the CLK signal.
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outc t
outg
CLK
GATE
OUT
V
OH
V
IH
V
IL
V
IH
V
OL
V
IL
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outg
t
outc
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
380 ns min
230 ns min
150 ns min
100 ns min
50 ns min
150 ns min
100 ns min
300 ns max
400 ns max