SUPER MICRO Computer P4SCT - Manual (Page 15)

Chapter 1: Introduction
1-9
1-2 Chipset Overview: Intel's Canterwood(875P) and
Canterwood ES (E7210)
Intel’s Canterwood Chipset (875P) and Canterwood ES (E7210) contains the
following main components: Canterwood Memory Controller Hub (MCH) and
the I/O Controller Hub (6300ESB-Hance Rapids ICH). These two compo-
nents are interconnected via Hub Interface.
Memory Controller Hub (MCH)
The Canterwood Memory Controller Hub (MCH) is designed to support Intel
PGA 478-pin Processors. The function of the Canterwood MCH is to arbi-
trate the flow of data transfer between system bus (FSB), system memory,
and Hub Interface. The Canterwood MCH supports 800 MHz FSB, 400/333
Memory Interface, 533 MHz FSB, 333/266 Memory Interface, and 400 MHz
FSB 266 MHz Memory Interface.
System Memory Interface
The Canterwood Memory Controller (MCH) supports two 64-bit wide DDR
data channels with bandwidth up to 6.4 GB/s (DDR400) in dual channel
mode. It supports 128-Mb, 256-Mb, 512-Mb, x8, X16 DDR. Maximum system
memory supports up to 4.0 GB for Dual-Channel. ECC/Non ECC unbuffered
DDR DIMMs are supported, but it does not support registered, mixed-mode
DIMMs.
Hance Rapids (6300ESB) ICH System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the 6300ESB (Hance Rapids) I/O Controller Hub (Hance Rapids ICH)
integrates many I/O functions.
The 6300ESB (Hance Rapids) integrates: 2-channel Ultra ATA/100 Bus Mas-
ter IDE Controller, two Serial ATA (SATA) Host Controllers, SMBus 2.0 Con-
troller, LPC/Flash BIOS Interface, PCI-X (66MHz) 1.0 Interface, PCI 2.2 Inter-
face and System Management Controller.
*Notes:
Intel 875P Canterwood (*P4SCT/P4SCT+II)
Intel E7210 Canterwood ES (*P4SCT+)