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Cpu 1 cpu 2 he-sl csb5, Ciob – Intel SERVER BOARD SDS2 User Manual

Page 85

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Intel® Server Board SDS2

Clock/Voltage Generation and Distribution

Revision 1.2

Order Number: A85874-002

71

HOST CLK

APIC CLK

48 MHz

14 MHz

PCI 33MHz CLK

PCI 66MHz CLK

CPU 1

CPU 2

HE-SL

CSB5

PCI 33MHz

CLK

BUFFER

SDRAM

CLK PLL

VGA

SDRAM 1

SDRAM 2

SDRAM 3

SDRAM 4

SDRAM 5

SDRAM 6

SDRAM

REGISTER 1

CIOB

PCI

66MHz CLK

BUFFER

PCI SLOT 2

PCI SLOT 1

PCI SLOT 6

PCI SLOT 5

NIC 1

NIC 2

SIO

BMC

U160 SCSI

PCI SLOT 3

PCI SLOT 4

IRQ 0

IRQ 1

cPLD

SDRAM

REGISTER 2

133 MHz

133 MHz

133 MHz

PCI

66MHz CLK

BUFFER

16 MHz

16 MHz

16 MHz

48 MHz

48 MHz

14 MHz

14 MHz

33 MHz

33 MHz

33 MHz

66 MHz

66 MHz

66 MHz

66 MHz

66 MHz

66 MHz

66 MHz

66 MHz

66 MHz

66 MHz

25 MHz

AGPFBCLK

CNBDCLKIN

PLLCLKFB0

CNBDCLKFB

CNBRDCLK

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

133 MHz

40 MHz

32 KHz

40 MHz

25 MHz

14.318 MHz

33 MHz

33 MHz

33 MHz

33 MHz

33 MHz

33 MHz

33 MHz

Figure 8. SDS2 Server Board Clock Generation/Distribution Diagram