Intel SERVER BOARD SDS2 - Manual (Page 62)

BIOS Intel® Server Board SDS2
Revision 1.2
Order Number: A85874-002
48
CP Beeps Reason
59 Initialize the POST display service
5A Display prompt “Press F2 to enter SETUP”
5B Disable L1 cache during POST
5C Test RAM between 512 and 640k
60 Test extended memory
62 Test extended memory address lines
64 Jump to UserPatch1
66 Configure advanced cache registers
67 Quick init of all AP's early in pos t
68 Enable external and processor caches
69 Initialize the SMM handler
6A Display external cache size
6B Load custom defaults if required
6C Display shadow message
6E Display non-disposable segments
70 Display error messages
72 Check for configuration errors
74 Test real-time clock
76 Check for keyboard errors
7A Test for key lock on
7C Set up hardware interrupt vectors
7D Intelligent system monitoring
7E Test coprocessor if present
81 POST device initialization routine
82 Detect and install external RS232 ports
83 Configure non-MCD IDE controllers
84 Initialize parallel ports
85 Initialize PC-compatible PnP ISA devices
86 Re-initialize on board I/O ports
87 Configure Mother Board Configurable Devices
88 Initialize BIOS Data Area
89 Enable Non-Maskable Interrupts
8A Initialize Extended BIOS Data Area
8B Test and initialize PS/S mous e
8C Initialize floppy controller
90 Initialize hard disk controller
91 Initialize local bus hard disk controller
92 Jump to UserPatch2
93 Build MPTABLE for multi-processor boards
94 Disable A20 address line
95 Install CD-ROM for boot
96 Clear huge ES segment register