Intel 80C188XL - Manual (Page 93)

BUS INTERFACE UNIT
3-12
Figure 3-11. Demultiplexing Address Information
Table 3-1. Bus Cycle Types
Status Bit
Operation
S2 S1 S0
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Instruction Prefetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Idle (passive)
4
I
I
STB
8
8
O
O ALE
Latched
Address Signals Signals From CPU
A19:16
AD15:8
AD7:0
8
8
I
3
LS2:0
O
4
LA19:16
LA7:0
LA15:8
S2:0
3
OE
I
STB O
OE
STB
OE
A1102-0A