Intel 80C188XL - Manual (Page 95)

BUS INTERFACE UNIT
3-14
Figure 3-12. Data Phase Signal Relationships
AD15:0
Write
AD15:0
Read
S2:0
CLKOUT
T2
T3
or TW
T4
or TI
RD/ WR
1
4 2
3
5
6
7
Valid
Read Data
Valid Write Data
NOTES:
1. TCLRL/CLWL, TCLOV : Clock low to valid RD/WR active, write data valid.
2. TCLSH : Clock low to status inactive.
3. TDVCL : Data input valid to clock low.
4. TCLRH/CLWH : Clock valid to RD/WR inactive.
5. TCLDX : Data input HOLD from clock low.
6. TWHDX : Output data HOLD from WR high.
7. TRHAV : Bus no longer floating from RD high.