Intel 80C188XL - Manual (Page 208)

8-13
INTERRUPT CONTROL UNIT
Figure 8-4. Interrupt Control Register for Internal Sources
Register Name: Interrupt Control Register (internal sources)
Register Mnemonic: TCUCON, DMA0CON, DMA1CON
Register Function: Control register for the internal interrupt sources
Bit
Mnemonic
Bit Name
Reset
State
Function
MSK Interrupt
Mask 1 Clear to enable interrupts from this source.
PM2:0 Priority
Level 111 Defines the priority level for this source.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
A1213-A0
15 0
P
M
0
P
M
1
P
M
2
M
S
K