Intel 80C188XL - Manual (Page 114)

3-33
BUS INTERFACE UNIT
Figure 3-29. Exiting HALT
3.6 SYSTEM DESIGN ALTERNATIVES
Most system designs require no signals other than those already provided by the BIU. However,
heavily loaded bus conditions, slow memory or peripheral device performance and off-board de-
vice interfaces may not be supported directly without modifying the BIU interface. The following
sections deal with topics to enhance or modify the operation of the BIU.
CLKOUT
AD15:0
[AD7:0]
ALE
[A15:8]
A19:16
Note 2
NOTES: 1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min).
2. Previous bus cycle value.
S2:0
BHE
RFSH
Note 2
NMI/INTx
Addr
Note 2
Note 2
Note 1
Valid
Address
Addr
A1517-0A