HP AMD Geode ECM-5510 - Manual (Page 46)

ECM-5510
46 ECM-5510 User’s Manual
2.4.19.1.3 Commands
Signal Signal Description
BALE
This is an active high signal used to latch valid addresses from the current bus
master on the falling edge of BALE. During DMA, refresh and alternate master
cycles, BALE is forced high for the duration of the transfer. BALE is driven by the
permanent master with a totem-pole driver.
IOR#
This is an active low signal driven by the current master to indicate an I/O read
operation. I/O mapped devices using this strobe for selection should decode
addresses SA [15:0] and AEN. Additionally, DMA devices will use IOR# in
conjunction with DACKn# to decode a DMA transfer from the I/O device. The
current bus master will drive this line with a tri-state driver.
IOW#
This is an active low signal driven by the current master to indicate an I/O write
operation. I/O mapped devices using this strobe for selection should decode
addresses SA [15:0] and AEN. Additionally, DMA devices will use IOR# in
conjunction with DACKn# to decode a DMA transfer from the I/O device. The
current bus master will drive this line with a tri-state driver.
SMEMR#
This is an active low signal driven by the permanent master to indicate a memory
read operation in the first 1MB of system memory. Memory mapped devices using
this strobe should decode addresses SA [19:0] only. If an alternate master drives
MEMR#, the permanent master will drive SMEMR# delayed by internal logic. The
permanent master ties this line to VCC through a pull-up resistor to ensure that it is
inactive during the exchange of bus masters.
SMEMW#
This is an active low signal driven by the permanent master to indicate a memory
write operation in the first 1MB of system memory. Memory mapped devices using
this strobe should decode addresses SA [19:0] only. If an alternate master drives
MEMR#, the permanent master will drive SMEMR# delayed by internal logic. The
permanent master ties this line to VCC through a pull-up resistor to ensure that it is
inactive during the exchange of bus masters.
MEMR#
This is an active low signal driven by the current master to indicate a memory read
operation. Memory mapped devices using this strobe should decode addresses
LA [23:17] and SA [19:0]. All bus masters will drive this line with a tri-state driver.
The permanent master ties this line to VCC through a pull-up resistor to ensure
that it is inactive during the exchange of bus masters.
MEMW#
This is an active low signal driven by the current master to indicate a memory write
operation. Memory mapped devices using this strobe should decode addresses
LA [23:17] and SA [19:0]. All bus masters will drive this line with a tri-state driver.
The permanent master ties this line to VCC through a pull-up resistor to ensure
that it is inactive during the exchange of bus masters.