KEPCO KLR Series Developers Guide - Manual (Page 119)

KLR-DEV 060713
B-17
FIGURE B-6. USING STATUS COMMANDS AND QUERIES
B.63 STATus:QUEStionable[:EVENt]? QUERY
STAT:QUES?
Syntax: Short Form: STAT:QUES[EVEN]? Long Form: STATus:QUEStionable[EVENT]?
Return Value: actual register value
Description: Indicates questionable events that occurred since previous STAT:QUES? query. Returns the
value of the Questionable Event register (see Table B-3). The Questionable Event register is a
read-only register which holds (latches) all events. Reading the Questionable Event register clears it.
(See example, Figure B-6.)
NOTE: Removing source power from the unit (e.g., setting POWER ON/OFF circuit breaker to OFF)
causes the unit to generate and store the PWR bit. Therefore the first query of the Questionable Event
Register after the unit is turned on will always show a PWR fault - this is normal.
NOTE: The following example assumes KLR 75-32 with limit model set for 75V, 16A and output
operating in voltage stabilization mode. See Figure B-3 for directions on programming limit
model settings.
volt:prot:max Sets OVP limit to maximum.
outp on Power supply output is on.
volt 20;curr 1 Power supply output is programmed to 20V, 1A.
syst:err? Returns 0, “No error” message.
stat:oper? Returns 1280, indicating that power supply has entered both CV
and CC modes during start-up.
stat:oper:enab 1312 Mask enabled for CV, CC, and WTG bits.
stat:oper:enab? Returns 1312 (1024 + 256 + 32), indicating CV, CC, and WTG bits
are set.
init:cont on Continuous triggers enabled.
stat:oper:cond? Power supply returns 288 (256 + 32), indicating power supply is in
constant voltage mode and Wait For Trigger is set.
stat:oper? Returns 32, CV mode bit cleared by prior query, but continuous
triggering results in WTG bit always being set.
volt 30 Output voltage programmed to 30V; current remains at 1A.
*stb? Return 128, Operation Status Summary bit is set.
stat:ques? Returns 16, loss of source power detected. (This event was set at
prior power-down of power supply and is retained for retrieval at
next power-up; reading the event register clears the bit.)
stat:ques:enab 3 Mask enabled for OVP and OCP bits (1 + 2).
stat:ques:enab? Returns 3 (1 + 2) indicating OVP and OCP bits are enabled.
volt:prot 25 Overvoltage protection limit set to 25V with output programmed to
30V, creating an OVP fault condition.
*stb? Returns 140, Operation, Questionable and Error Status bits were
set.
syst:err? Returns -305 “Voltage Protection Fault”
stat:ques? Returns 1, overvoltage protection error detected.
stat:ques? Returns 0, Reading prior register cleared register contents.
stat:ques:cond? Returns 1, power supply is in overvoltage protection.
outp? Returns 0, output set to off when overvoltage error detected.
stat:pres Operation enable and Questionable enable registers reset.
stat:ques:enab? Returns 0, Questionable Condition Enable register reset prevents
any questionable events from being reported.
stat:oper:enab? Returns 0, Operation Condition Enable register reset prevents
any operational events form being reported.