KEPCO KLP Series Developer's Guide, Rev 1 - Manual (Page 122)

B-16
KLP 031113
B.60 STATus:OPERation:ENABle? QUERY
STAT:OPER:ENAB?
Syntax: Short Form: STAT:OPER:ENAB? Long Form: STATus:OPERation:ENABle?
Return Value: 0 to 1313 (1 + 32 + 256 + 1024).
Description: Reads Operation Enable Register (see Table B-2). Returns value of Operation Enable Register
bits. Bit set to 1 = function enabled (active, true); bit reset to 0 = function disabled (inactive, false).
(See
examp le, Figure B-6.)
B.61 STATus:OPERation[:EVENt]? QUERY
STAT:OPER?
Syntax: Short Form: STAT:OPER[:EVEN]? Long Form: STATus:OPERation[:EVENt]?
Return Value: 0 to 1313 (1 + 32 + 256 + 1024).
Description: Indicates changes in conditions monitored by Operational Event Register. Returns the value of
the Operation Event register. The Operation Event register is a read-only register which holds
(latches) all events that occur. Reading the Operation Event register clears it. (See example, Figure B-
6.)
B.62 STATus:PRESet COMMAND
STAT:PRES
Syntax: Short Form: STAT:PRES Long Form: STATus:PRESet
Description: Disables reporting of all status events. This command sets all bits of the Operation Condition
(Table B-2) and Questionable Condition Enable Registers to 0, preventing all status events from being
reported. (See example, Figure B-6.)
FIGURE B-6. USING STATUS COMMANDS AND QUERIES
NOTE: The following example assumes KLP 75-33-1200 with virtual model set for 75V, 16A and
output operating in voltage stabilization mode. See Figure B-3 for directions on program-
ming virtual model limits.
outp on Power supply output is on.
volt 20;curr 1 Power supply output is programmed to 20V, 1A.
syst:err? Returns 0, "No error" message.
stat:oper? Returns 1280, indicating that power supply has entered both CV
and CC modes during start-up.
init:cont on Continuous triggers enabled.
stat:oper:cond? Power supply returns 288 (256 + 32), indicating power supply is in
constant voltage mode and Wait For Trigger is set.
stat:oper? Returns 32, CV mode bit cleared by prior query, but continuous
triggering results in WTG bit always being set.
stat:oper:enab 1312 Mask enabled for CV, CC, and WTG bits.
stat:oper:enab? Returns 1312 (1024 + 256 + 32), indicating CV, CC, and WTG
bits are set.
volt 30 Output voltage programmed to 30V; current remains at 1A.
*stb? Return 128, Operation Status Summary bit is set.
stat:ques? Returns 16, loss of source power detected. (This event was set
at prior power-down of power supply and is retained for retrieval
at next power-up; reading the event register clears the bit.)
stat:ques:enab 3 Mask enabled for OVP and OCP bits (1 + 2).
stat:ques:enab? Returns 3 (1 + 2) indicating OVP and OCP bits are enabled.
volt:prot 25 Overvoltage protection limit set to 25V with output programmed to
30V, creating an OVP fault condition.
*stb? Returns 136, Operation and Questionable Status bits were sets.
stat:ques? Returns 1, overvoltage protection error detected.
stat:ques? Returns 0, Reading prior register cleared register contents.
stat:ques:cond? Returns 1, power supply is in overvoltage protection.
outp? Returns 0, output set to off when overvoltage error detected.
stat:pres Operation enable and Questionable enable registers reset.
stat:ques:enab? Returns 0, Questionable Condition Enable register reset prevents
any questionable events from being reported.
stat:oper:enab? Returns 0, Operation Condition Enable register reset prevents
any operational events form being reported.