Sensoray 826 - Manual (Page 66)

determines the pulse duration and PGAP determines the gap time between pulses. The RST signal is not internally
connected to the host computer's system reset input; if desired, this must be implemented by externally routing the selected
DIO pin to the computer's reset input.
9.1.2 Reset Out Circuit
Two solid state relays (SSRs) are provided for controlling external reset circuits. Both SSRs are energized when the
watchdog RST generator is asserting its output signal. One SSR has normally open contacts and the other normally closed
contacts. The SSRs are galvanically isolated from other board circuitry.
9.1.3 Initialization
Before enabling the watchdog, the program must initialize it by writing to the configuration register and the five timing
control registers (DELAY0-DELAY2, PWIDTH, and PGAP). This is done by calling S826_WatchdogConfigWrite. The
DELAY registers determine the time intervals of their three associated timers, whereas the PWIDTH and PGAP registers
determine the timing of the RST output signal.
9.2 Connector P2
Connector P2 interfaces external circuitry to the Reset Out solid state relay. Refer to the block diagram in section 9.1 for
connector pinout.
9.3 Programming
9.3.1 S826_WatchdogConfigWrite
The S826_WatchdogConfigWrite function configures the watchdog system.
int S826_WatchdogConfigWrite(
uint board, // board identifier
uint cfg, // configuration flags
uint timing[5] // time intervals
);
Parameters
board
826 board number. This must match the settings of the board's dip switches as described in section 2.2.
cfg
Configuration flags: '1' = enable feature, '0' = disable feature.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GSN 0 SEN NIE PEN 0 OEN
Flag Function
GSN Generate host system NMI upon Timer1 event.
SEN Activate safemode upon Timer0 event.
NIE Connect Timer1 event signal to the DIO_out routing matrix NMI net.
PEN Enable RST output to pulse (vs. continuous active level).
OEN Connect RST generator to the DIO_out routing matrix RST net.
timing
Pointer to array of five quadlets that define the watchdog's time intervals. Each quadlet is written to one of the
watchdog timing control registers as shown below. All times are specified as multiples of 20 nanoseconds. For
example, use the value 50,000,000 for a one-second time interval.
826 Instruction Manual 61 Watchdog Timer