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Sensoray 826 User Manual

Page 49

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NR

Preload permissive. Typically used for “one-shot” pulse generator applications.

0

Allow preloading any time. This can be used for applications such as a retriggerable one-shot.

1

Allow preloading only when counts equal zero. This can be used for applications such as a non-retriggerable
one-shot. This applies to both hardware- and software-induced (via S826_CounterPreload function) preloads.

UD

Count direction

0

Normal count direction.

1

Reverse count direction.

BP

Preload toggle enable.

0

Use only Preload0. The Preload1 register will not be used.

1

Use both preload registers. This is typically used for PWM output.

OM

ExtOut mode. Determines when the channel's ExtOut output signal is active. The ExtOut signal may
be routed to a DIO pin by calling S826_DioOutputSourceWrite.

0

Output always inactive.

1

Output pulses active upon Compare register snapshot.

2

Output active when Preload1 register is selected. This is typically used for PWM output.

3

Output active when the counts are not zero; useful for pulse generator applications.

4

Output active when the counts are zero; useful for watchdog timer applications.

OP

ExtOut signal polarity.

0

Normal polarity

1

Inverted

TE

Count enable trigger. Determines event(s) that will cause counting to be enabled.

0

Enable counting at start-up (i.e., when S826_CounterModeWrite is called to switch to running mode).

1

Enable counting upon Index leading edge.

2

Enable counting upon preload.

3

reserved -- do not use.

TD

Count disable trigger. Determines event(s) that will cause counting to be disabled.

0

Never disable counting.

1

Disable counting upon Index falling edge.

2

Disable counting upon zero counts reached.

3

reserved -- do not use

K

Clock mode.

0

External single-phase clock, increment on ClkA rising edge.

1

External single-phase clock, increment on ClkA falling edge.

2

Internal 1 MHz clock, increment every microsecond.

3

Internal 50 MHz clock, increment every 40 nanoseconds.

4

Link to adjacent channel's overflow/underflow outputs to this channel's overflow/underflow inputs (see
“Cascading”). The adjacent channel's overflow/underflow output signals will cause this channel to
increment/decrement. For channel 0, channel 5 is the adjacent channel; for all other channels N, the adjacent
channel is N-1.

5

External quadrature clock, x1 multiplier.

6

External quadrature clock, x2 multiplier.

7

External quadrature clock, x4 multiplier.

826 Instruction Manual

44

Counters