Sensoray 826 - Manual (Page 34)

7.1.5 Snapshots
A “snapshot” consists of three values that are simultaneously sampled in response to a trigger: the counts contained in the
counter core, the timestamp (which indicates the time the snapshot was captured), and a set of “reason” flags that indicate
the type of event (or types of events, if multiple events occurred at the same time) that triggered the snapshot.
Snapshots are stored in the Snapshot FIFO. Snapshots are written to the FIFO as they occur, whereas the host may read
them from the FIFO at any convenient time. The FIFO stores up to 16 snapshots. When the FIFO is full, a subsequent
trigger will cause a new snapshot to be stored in the FIFO and the oldest snapshot in the FIFO will be deleted.
The Hold register caches a snapshot while it is being read by the host. The snapshot timestamp and reason code are copied
to the Hold register when the snapshot counts are read. The host will then read the cached timestamp and reason code from
the Hold register, thus ensuring the three snapshot values will remain correlated if a FIFO overflow occurs while the
snapshot is being read.
A snapshot may be captured in response to various types of hardware and software triggers. All of the hardware trigger
types can be individually enabled through the snapshot configuration register. Snapshots may be triggered when:
• The S826_CounterSnapshot function is called (i.e., a “soft” snapshot).
• The counter matches a compare register.
• Transitions occur on the Index input.
• Transitions occur on the ExtIn input.
• The counter reaches zero counts.
• A quadrature clock encoding error is detected. Once this happens, no further error-triggered snapshots can be captured
until the error is cleared. The resulting error snapshot enables the application to determine the counts at the moment the
error occurred. See S826_CounterSnapshotRead for further information.
Multiple counters can use the same snapshot trigger source or sources. For example, two or more counters could be
configured to capture snapshots in response to a signal from a common DIO channel, thus enabling an external signal to
simultaneously trigger snapshots on all affected counters. Similarly, a virtual digital output channel could be used as a
common trigger, thereby allowing software to simultaneously trigger snapshots on the affected counters.
7.1.6 Preloading
The counter core can be “preloaded” (parallel-loaded) from the Preload0 and Preload1 registers in response to various
hardware and software preload triggers. All of the hardware triggers can be individually enabled through the mode register.
Preloads may be triggered:
• When the S826_CounterPreload function is called (i.e., a “soft” preload).
• When the channel state switches from halted to running.
• When the counter reaches zero counts.
• When the counter matches a compare register.
• When transitions occur on the Index input.
• While the Index input is held at its active level. This has the effect of holding the counter core at the preload value while
Index is asserted.
The mode register's BP bit specifies whether both preload registers will be used or only Preload0. Preload0 is active
(selected) by default when the channel state switches from halted to running. When a preload occurs, the core is first
preloaded from the preload register and then the active register selector will change.
The preload mechanism behaves as shown in the following table. For example, if both preload registers are being used
(BP=1) and a preload occurs because the counts reached zero, the core will be preloaded from the active preload register
and then the other preload register will be activated.
826 Instruction Manual 29 Counters