Sensoray 826 - Manual (Page 54)

The channel's DIO_out signal router consists of a data selector that can route either the DIO output register or an alternate
source to the I/O pin. The pin will function as a general-purpose digital output when the DIO output register is selected. If
the alternate source is selected, the pin state will be controlled by the alternate signal, but all DIO input functions (read,
edge detection) will continue to operate normally. Each DIO is associated with a specific alternate source as explained in
S826_DioOutputSourceWrite.
The DIO_in routing matrix connects the sampled DIO pin signal to other interfaces. The ADC trigger input and the six
counter ExtIn inputs are connected to the DIO_in matrix so that any of these signals can be sourced from a DIO pin. When
a DIO signal is routed to another interface via the DIO_in matrix, all of the DIO channel's input and output functions will
continue to operate normally.
8.1.2 Safemode
Safemode is activated when the SAF signal (see Figure 7) is asserted. When operating in safemode, the DIO pin state is
determined by the Safe Enable and Safe Data registers: when Safe Enable equals '1', the pin will be driven to the fail-safe
value stored in Safe Data; when Safe Enable equals '0' the pin will output its normal runmode signal.
Upon board reset, the Safe Enable register is set to '1' so that the DIO pin will exhibit fail-safe behavior by default (i.e., it
will output the contents of the Safe Data register when SAF is asserted). Fail-safe operation can be disabled for a DIO pin
by programming its Safe Enable register to '0'.
The Safe Data register is typically programmed once (or left at its default value) by the application when it starts, though it
may be changed at any time if required by the application. It can be written to only when the SWE bit is set to '1'. See
“Safemode Controller” for more information about safemode.
8.1.3 Edge Capture
Every DIO channel includes an edge detection circuit and a capture flag register. When edge capturing is enabled, a
channel's capture flag will be set when an edge is detected on its I/O pin. Each channel may be programmed to capture
rising edges, falling edges, or both edges, or capturing may be disabled.
The API allows capture flags to be monitored by polling or, if the application is event driven, the calling thread can block
while it waits for captured events. When blocking on edge capture events, the calling thread can specify a set of capture
flags to wait for, and it can wait for either all of the events or any one event in the set.
When read by the host, capture flags are reset but remain enabled to capture future events. Edge events that occur on a
channel while its capture flag is set will be lost. An input signal must hold for at least 20 ns after a transition for the
transition to be reliably detected.
8.1.4 Pin Timing
The DIO subsystem is a fully synchronous system that is controlled by a 50 MHz sampling clock. The DIO pin drivers are
updated and pin receivers are sampled once per cycle. As a result, outputs cannot change faster than the cycle time and
inputs cannot be sampled faster than the cycle time.
Output registers are organized as two 24-channel groups. When these registers are written (via S826_DioOutputWrite),
channels 0-23 will change simultaneously and channels 24-47 will also change simultaneously, but these two 24-channel
groups are not guaranteed to change output states at the same time. Also, a DIO pin does not change output state
immediately when its signal source (DIO output register or counter ExtOut) changes; it will be delayed for 20 ns due to the
sampling clock.
When used as inputs, all 48 DIO channels are sampled simultaneously every 20 ns. As a result, the received signal on a
DIO pin may be delayed up to 20 ns en route to its destination (e.g., DIO edge detector or read data, counter ExtIn input, or
ADC trigger input), and input signal pulses shorter than 20 ns may not be recognized. The host reads pin states (via
S826_DioInputRead) as two 24-channel groups (channels 0-23 and 24-47) in two separate read cycles. Consequently,
channels within each group are guaranteed to be sampled simultaneously, but the two groups are not guaranteed to be
associated with the same sample clock.
826 Instruction Manual 49 Digital I/O