Chapter 9: watchdog timer, 1 introduction, 1 operation – Sensoray 826 User Manual
Page 65: Watchdog timer, Introduction, Operation
Chapter 9: Watchdog Timer
9.1 Introduction
The model 826 board has a multistage watchdog timer that can activate the board's safemode system and generate service
requests. The watchdog has three timer stages that generate timeout events in sequence according to user-defined timing.
Each event is associated with an output signal. Typically, the event signals are utilized in such a way that successive events
will generate service requests of progressively higher priority.
Figure 8: Watchdog system
9.1.1 Operation
When the watchdog system is disabled (default upon board reset), the three timers are halted and loaded from their
associated DELAY registers. When the system becomes enabled (EN='1') by calling S826_WatchdogEnableWrite, initially
only Timer0 is enabled so that it will count down towards zero while the other timers remain idle. During normal operation,
the program regularly “kicks” the watchdog by writing to the Kick port, thus reloading Timer0 from DELAY0 before it can
count down to zero.
If a fault condition prevents the program from kicking the watchdog, Timer0 will count down to zero and assert its timeout
(TO) signal. After this event occurs, all subsequent kicks will be ignored. This event enables Timer1 and generates an
interrupt request, and if SEN='1', it switches all control outputs to fail-safe states by triggering the safemode system. The
program can wait for the interrupt by calling S826_WatchdogEventWait.
Timer1 asserts its TO signal upon counting down to zero. This event enables Timer2 and, if NIE='1', it asserts the NMI net
of the DIO_out signal routing matrix, which in turn may route the net to a DIO pin (see S826_DioOutputSourceWrite).
When GSN='1', a Timer1 event will cause the board to issue a PCI Express fatal error message; this can be used to generate
a system non-maskable interrupt request if the system has been appropriately configured. Refer to your system
documentation for information about generating NMI in response to a PCI Express fatal error message.
Timer2 asserts its TO signal upon counting down to zero, thus activating the RST signal generator. If OEN='1', the RST
generator's output is routed to the RST net of the DIO_out signal routing matrix and to the board's Reset Out circuit. The
RST generator can produce a continuous (non-pulsed) output or pulsed output. When generating a pulsed output, PWIDTH
826 Instruction Manual
60
Watchdog Timer
RST
Generator
DELAY2
Reg
Timer2
Timer1
Timer0
PWIDTH
Reg
Config
Reg
PGAP
Reg
DELAY1
Reg
DELAY0
Reg
Kick
Port
Internal
Data Bus
SEN
Safemode Trigger
(to safemode controller)
To DIO_out Signal
Routing Matrix
NIE
OEN
IRQ
EN
32
32
32
32
32
Out
D
Kick
E
E
E
E
D
D
TO
DB
DA
TO
TO
GSN
NMI
RST
NMI
To Host
Interrupt
System
PEN
Mode
COM
N.O.
N.C.
1
3
2
P2
Reset
Out