Measurement Computing CIO-PDMAxx - Manual (Page 26)

Data Transfer
CIO-PDMA16 Interrupt, DMA or software polled
CIO-PDMA32 From 512 sample FIFO via REPINSW,
interrupt, DMA or software polled
DMA
CIO-PDMA16 Channel 1 or 3, software selectable
CIO-PDMA32 Channel 5, 6, or 7,software selectable
Throughput
CIO-PDMA16 250K Bytes, 125K Words / sec synchronous
CIO-PDMA32 (DMA) 400K Bytes, 200K Words / sec synchronous
CIO-PDMA32 (REPIN/OUTS) 1500K Bytes, 750K Words / sec
synchronous
Interrupts
CIO-PDMA16 Levels 2 - 7, software-selectable
CIO-PDMA32 Levels 2 - 15, software-selectable
Interrupt enable Programmable
Interrupt sources External (Int In, positive or negative edge
software-selectable), DMA terminal count,
Counter / Timer terminal count,
software-selectable
Counter section
Counter type
CIO-PDMA16 82C54
CIO-PDMA32 82C54 emulator
Configuration 3 down-counters per 82C54, 16 bits each
Counter 0 - Internal pacer, lower divider (mode 2 only
for CIO-PDMA32)
Source: 10 MHz oscillator
Gate: Wired to counter 1 gate, pulled high
through 10k resistor. Available at user
connector (Timer Gate In)
Output: Wired to counter 1 and counter 2 clock
inputs
Counter 1 - Internal pacer, upper divider (mode 2 only
for CIO-PDMA32)
Source: Counter 0 output
Gate: Wired to counter 0 gate, pulled high
through 10k resistor. Available at user
connector (Timer Gate In)
Output: Wired through inverter to user connector
(Timer Out). Program-selectable as DMA
Request source (internal pacer)
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